1. Field
Example embodiments are directed to methods of forming fine patterns of semiconductor devices, for example, a method of forming fine patterns of a semiconductor device using hardmask patterns at a fine pitch.
2 . Description of the Related Art
To fabricate highly integrated semiconductor devices, reducing pattern size may be necessary. To integrate elements in a relatively small area, the individual elements may have relatively small dimensions. This may be possible by reducing the pitch of a desired pattern to be formed, where the pitch is the sum of the width and the gap between adjacent patterns. Currently, the decrease of the design rule of semiconductor devices may be limited due to photolithographic resolution restrictions. For example, forming a desired pattern with a fine pitch may be limited because of the resolution restrictions of photolithography for forming an isolation region defining an active region in a substrate and forming a line and space (L/S) pattern.
To overcome photolithographic resolution restrictions, methods of forming hard mask patterns with a fine pitch using double patterning may be used.
In this example, simultaneous formation of given patterns may be desired in a region having a relatively high pattern density, such as a cell array region, or in a region having a relatively low pattern density, such as a peripheral circuit region or core region.
When applying double patterning, if patterns with different pitches are simultaneously formed in respective regions, each having desired pattern densities or pattern widths that may be different from one another, differences of etch rates and etch depths in respective regions caused by the difference in pattern densities or pattern widths in respective regions may become problematic.